EDN

ESC – New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces

Mountain View, Calif. – Synopsys, Inc. today announced the availability of the high-performance DesignWare Universal DDR Protocol and Memory Controllers, both supporting the DDR2, DDR3, Mobile DDR and ...
Business Wire

Silvaco and OPENEDGES Announce Availability of Integrated DDR Controller and PHY IP Solutions

SANTA CLARA, Calif. & SEOUL, South Korea--(BUSINESS WIRE)--Silvaco, Inc., a leading supplier of EDA software and design IP, today announced a collaboration with OPENEDGES Technology, Inc., a leading ...
Electronic Design

PWM Controller IC Aims At DDR Memory Arrays

The IRU3038 synchronous pulse-width modulation (PWM) controller IC handles the termination-voltage requirements of double-data-rate (DDR) memory arrays. By ...
Electronic Design

Mobileye sees Denali DDR controller IP in automotive systems

Mobileye N.V. (www.mobileye.com) has licensed Databahn DDR memory controller intellectual property from Denali Software (www.denali.com) for use in Mobileye’s EyeQ2 Vision system-on-chip. Nov. 27, ...
Semiconductor Engineering

Advantages Of LPDDR5: A New Clocking Scheme

Innovative new clocking schemes in the latest LPDDR standard enable easier implementation of controllers and PHYs at maximum data rate as well as new options for power consumption. Earlier this year, ...
Semiconductor Engineering

DDR Memory Test Challenges From DDR3 to DDR5

Cloud, networking, enterprise, high-performance computing, big data, and artificial intelligence are propelling the development of double data rate (DDR) memory chip technology. Demand for lower power ...
EDN

New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces

MOUNTAIN VIEW, Calif., April 28 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and ...